The present invention relates generally to the formation of solder bumps on an integrated circuit device, and more particularly, to the formation of solder bumps having improved height and reliability.
Faster, reliable, and higher-density circuits at lower costs are the goals for integrated circuit (IC) packaging. Conventional wirebond technology, the most common method for electrically connecting aluminum bonding pads on a chip surface to the package inner lead terminals on the lead-frame or substrate has proven to be low cost and reliable. But for the future, packaging goals will be met by increasing the density of chips and reducing the number of internal interconnections. Packages with fewer interconnecting links lower potential failure points, reduce the circuit resistance, and reduce interconnect capacitance, which affects electrical performance. The need to reduce the IC package to fit end-user applications (e.g., smart cards, palmtop computers, camcorders, and so on) is driving the new packaging designs that reduce size and overall profile. This reduction is offset by the need for handling larger amounts of parallel data lines, therefore driving the need to increase package input/output requirements with more leads.
Advanced packaging designs are regularly introduced to solve packaging challenges. One such advanced package design is flip chip. Flip chip is a packaging method of mounting the active side of a chip (with the surface bonding pads) toward the substrate (i.e., upside down placement of the bumped die relative to the wirebonding approach—thus the reason for the term “flip” chip). It provides the shortest path from the chip devices to the substrate and low cost interconnection for high I/O counts and high volume automated production. There is also a reduction in weight and profile since leadframes or plastic packages are often not used. Flip chip technology uses solder bumps—usually formed from tin/lead solder in a 5% Sn and 95% Pb ratio—to interconnect the chip bonding pads to the substrate.
There are several methods known to those skilled in the art for producing solder bumps on a semiconductor device. FIGS. 1A–1E illustrate a prior art method of forming a bump on a substrate of a semiconductor wafer. As shown in FIG. 1A, a semiconductor wafer 10 is provided having a base silicon substrate 12 with metal interconnect layers (not shown) overlying substrate 12 and an upper passivation layer 14, which may be one or more layers, that extends partially over a bond pad or contact pad 15 located on the upper surface of the semiconductor wafer 10. Passivation layer 14 has an opening overlying contact pad 15 so that electrical contact to an external circuit may be made from the semiconductor wafer 10. Contact pad 15 may be made from any of a variety of metals, such as aluminum, aluminum alloys, copper, and copper alloys. Typically, a under bump metallurgy (UBM) layer 16 is provided over the entire upper surface of semiconductor wafer 10 and over the upper surface of contact pad 15. UBM layer 16 may be composed of a plurality of individual layers of a variety of different metals and may be deposited by any of a variety of methods including electroless plating, sputtering, or electroplating. As shown in FIG. 1B, thereafter, a photoresist layer 22 is thereafter deposited over UBM layer 16 and patterned to provide an opening 24 overlying contact pad 15 on semiconductor wafer 10. Thereafter, an extra UBM layer 26 may be deposited by conventional methods such as electroplating over UBM layer 16. An electrically conductive material (e.g. solder) may then be deposited in opening 24 and on top of extra UBM layer 26 as shown in FIG. 1C to form a column of solder material 30. As shown in FIG. 1D, after the removal of the photoresist layer 22, the UBM layer 16 is etched through by a reactive ion etch (RIE) process, for example, to the underlying passivation layer 14 using the solder column 30 as an etching mask. The solder column 30 is then heated to reflow to form a solder bump 32 over semiconductor wafer 10 as shown in FIG. 1E.
Part of the standard process for forming a solder bump is the reflow step where the solder column 30 is gently heated to ensure its adhesion to the underlying UBM layer 16. As a result of this, the solder column 30 assumes a spherical shape (due to surface tension forces) and the solder column 30 becomes a solder bump 32, as illustrated in FIG. 1E. This leads to the diameter of the solder bump 32 being larger than the width of the base UBM layer 16. Furthermore, this creates a sharp angle between solder bump 32 and underlying UBM layer 16. The large solder bump diameter becomes a disadvantage in the manufacture of fine pitch bumping due to the concerns of solder bump bridging leading to short circuit in the integrated circuit. The trend in the semiconductor industry is to reduce the pitch of the solder bump arrays in order to accommodate higher level of circuit integration in integrated circuit devices that require greater interconnection densities. The sharp angle degrades the solder bump joint integrity and reliability and consequently, more bump protection is needed in flip chip packaging.
For these reasons and other reasons that will become apparent upon reading the following detailed description, there is a need for an improved method for forming solder bumps and solder bump structures that do not have the drawbacks or shortcomings of the conventional methods for forming solder bumps or solder bump structures.